FPGA

Bluehive — A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation

by Paul Fox

Presented at FCCM 2012

Bluehive is a custom 64-FPGA machine targeted at scientific simulations with demanding communication re- quirements.... more Bluehive is a custom 64-FPGA machine targeted at scientific simulations with demanding communication re- quirements. Bluehive is designed to be extensible with a recon- figurable communication topology suited to algorithms with demanding high-bandwidth and low-latency communication, something which is unattainable with commodity GPGPUs and CPUs. We demonstrate that a spiking neuron algorithm can be efficiently mapped to Bluehive using Bluespec SystemVerilog by taking a communication-centric approach. This contrasts with many FPGA-based neural systems which are very focused on parallel computation, resulting in inefficient use of FPGA resources. Our design allows 64k neurons with 64M synapses per FPGA and is scalable to a large number of FPGAs.

A Novel Automated Experimental Approach for the Measurement of On-Chip Speed Variations through Dynamic Partial Reconfiguration

by Hasan Baig

Hasan Baig, Jeong-Gun Lee and Jeong-A Lee

Tracking Control Using the Strip-wise Affine Transformation: An Experimental SoC Design

by George Moustris

Co-authored with Kyriakos. M. Deliparaschos, and Spyros. G. Tzafestas

This paper presents the analysis and application of the strip-wise affine map to the path following task for... more This paper presents the analysis and application of the strip-wise affine map to the path following task for autonomous non-holonomic mobile robots. The mapping was implemented on a Spartan 3-1500 FPGA board with the use of VHDL and advanced EDA tools and was used in field experiments on a Kheperea II differential robot. A fully parameterized DFLC previously published by the author has been tailored accordingly for the needs of this design implementation. The implemented SoC primarily comprises of the SLC core that computes the strip-wise affine transformation, while the DFLC core is mainly responsible for the control of the Kephera II robot. Other cores incorporated into the SoC, such as an UART core and LCD driver, allow for the communication with the Robot and the Matlab GUI environment as well as low level system messaging display.

SIGNAL PROCESSING FOR A LASER BASED AIR DATA SYSTEM IN COMMERCIAL AIRCRAFTS

by Theodoros Semertzidis

Hardware-Software Co-design Architecture for Snort NIDS Detection Engine

by Adeel Hashmi

In Proceedings of the first MMU-RD-10 Science and Engineering Research and Development Conference, Manchester, December, 2010 (ISBN: 978-1-905476-54-1).

Improvements in computer network transmission rates
have placed high computational demands on Network... more Improvements in computer network transmission rates
have placed high computational demands on Network Intrusion
Detection Systems (NIDS) such that existing NIDS
software packages such as Snort [1] that perform computationally significant malware pattern search or Deep Packet Inspection (DPI) in its Detection Engine (DE) component
can only sustain a maximum data rate of approximately
750Mbps [2] on a general purpose processor under test
condition [3]. In this paper, we present the design of novel
DE architecture for high speed DPI on a hybrid Hardware-
Software co-designed platform prototyped on a Field Programmable Gate Array (FPGA) with a softcore MicroBlaze
processor. The platform provides opportunities to provide
custom hardware support to accelerate the execution of DE
component. The novel DE architecture and its performance
results are presented. This DE performs malware pattern
search in the packet payload content upto 2.49Gbps which
is supported by memory efficient Bloom filter search approach
that enable compact storage of the largest number
of 7876 unique malware patterns in fast access on-chip
FPGA local memory (FPGA block RAM).

Hardware/Software Co-design Platform for Network Intrusion Detection System

by Adeel Hashmi

In Proceedings of the Third International Conference on Internet Technologies and Applications, Wales, September, 2009 (ISBN: 978-0-946881-65-9).

Improvements in computer network transmission rates have placed high computational demands on Network Intrusion... more Improvements in computer network transmission rates have placed high computational demands on Network Intrusion Detection Systems (NIDS) such that existing NIDS software packages can only sustain a maximum data rate of approximately 566 Mbps[1] on an Intel Xeon 2.0 GHz dual-core general purpose processor. Also, the current state of the art in commercial Network Intrusion Prevention Systems (NIPS) offer upto 4Gbps speed [2]. In this paper, we present the design of novel NIDS prototype architecture on a Hardware/Software Co-designed platform implemented on a Field Programmable Gate Array (FPGA) with a soft core MicroBlaze processor. The platform provides opportunities to provide custom hardware support to accelerate the execution of NIDS computations that are inefficiently supported by general purpose processor instruction sets. The software architecture of the SNORT [3]
NIDS and its computational characteristics on a PC are presented and compared with those of our
preliminary SNORT port executing on a Xilinx MicroBlaze core [4] on an FPGA. This system performance is approximately 1.7 times better than Snort executing on a general purpose processor on PC when comparing processor cycles rather than wall clock time.

FPGA BASED VIBRATION CONTROL OF A MASS VARYING TWO-DEGREE OF FREEDOM SYSTEM

by Prashant Kumar Tripathi

Study of FPGA Based Vibration Control of a Mass Varying Two-Degree of Freedom System

by Prashant Kumar Tripathi

Stochastic-based pattern-recognition analysis

by Josep L. Rossello

Hardware implementation of stochastic-based Neural Networks

by Josep L. Rossello

Designing an IP-Core for Edge Detection in Monochrome Image Using the Sobel Operator

by Jody Maick Matos

Co-authored with Fladmy Alvez and Anfranserai Dias. Published in 11th Microelectronics Students Forum (SFotum 2011).

The integrated circuit designs are reaching high levels of complexity. Due to the great importance of these devices... more The integrated circuit designs are reaching high levels of complexity. Due to the great importance of these devices nowadays they are performing increasingly complex functions. In this case the use of methodologies and tools in development process such devices are essential, as well as projecting Systems-on-Chip (SoC) with reusable IP-Cores. This paper describes the designing of a Soft IP-Core for edge detection in monochrome images using the Sobel Operator, applying the ipPROCESS methodology, a Brazilian initiative in order to create a standard and enhance the development of integrated circuit design in the country.

PROCESADOR PARALELO DE FFT IMPLEMENTADO EN FPGA

by Pablo Sonna

RTOS Hardware Coprocessor Implementation in VHDL

by Carlos Ferreira

This paper discusses the benefits of using a hardware coprocessor
to improve the determinism and performance of... more This paper discusses the benefits of using a hardware coprocessor
to improve the determinism and performance of a
Real-Time Kernel. The proposed coprocessor was modeled
with the VHDL hardware description language and implemented
in a FPGA (Field-Programmable Gate Array). It
is able to manage (schedule, preempt and dispatch) several
tasks, either periodic or aperiodic. The preemption of the
task running on the Central Processing Unit (CPU) is performed
through an interrupt line that connects the coprocessor
to the CPU. External interrupt sources are connected
to the coprocessor to allow a controlled activation and dispatching
of the respective service tasks.
The validation and benchmarking of the real-time kernel
with the co-processing unit, shows a significant increase on
the determinism and performance of the system, when compared
with the same system but without the help of the coprocessing
unit, i.e. running fully in software.

Actualización de la currícula Incorporación de la lógica programable en ingenierías

by Pablo Cayuela

JIDIS 2007, Argentina
Jornadas de Investigación y Desarrollo en Ingeniería de Sistemas 2007, Universidad Tecnológica Nacional, Facultad Regional Córdoba, Argentina

Resumen

En este trabajo, se propone modificar ligeramente el contenido de ciertas materias de las carreras... more Resumen

En este trabajo, se propone modificar ligeramente el contenido de ciertas materias de las carreras de Ingeniería Electrónica e Ingeniería en Sistemas de Información, de la Universidad Tecnológica Nacional, para adecuarlas a la renovación tecnológica de la electrónica de consumo actual, que si bien aún no ha inundado Argentina, al punto de hacer absolutamente obsoletas las técnicas digitales discreta y de integración moderada, y las metodologías de diseño de sistemas, no va a pasar demasiado antes de que sea necesario un cambio radical en la industria, en el mercado de consumo masivo, y si seguimos a este ritmo, en última instancia en la educación técnica y tecnológica de nivel terciario-universitario.

FPGA Based Fuzzy Link Cost Processor for Energy-Aware Routing in Wireless Sensor Networks-Design and Implementation

by Tarique Haider

A fully digital hysteresis current controller for an active power filter

by Dave Ingram

A novel digital hysteresis current controller for an active power filter

by Dave Ingram

160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array(FPGA)

by Isaac Li

Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric

by Turhan Karadeniz

Análise de Somadores em FPGA ALTERA com Aplicação em uma Unidade Aritmética em Ponto Flutuante

by João Carlos Nunes Bittencourt

Co-authored with Fernando Alberto Correia dos Santos Junior and Delmar Broglio Carvalho, published in Proceedings of XXIV CRICTE, Rio Grande/RS FURG: 2010

A busca crescente por alternativas para aumentar o desempenho de operadores aritméticos implementados em... more A busca crescente por alternativas para aumentar o desempenho de operadores aritméticos implementados em hardware  torna cada vez mais importante a análise dos custos destas implementações em termos de desempenho e consumo de recursos físicos. Este artigo apresenta os resultados do desenvolvimento dos somadores Ripple Carry, Carry Select, Carry Look-ahead e o Macro Function. Essa análise foi realizada com base no projeto de uma unidade de ponto flutuante sintetizada em uma FPGA, de acordo com o padrão IEEE 754-2008, para precisão simples e meia precisão simples.